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1 ? HIP6018B advanced pwm and dual linear power control the HIP6018B provides the po wer control and protection for three output voltages in hi gh-performance microprocessor and computer applications. the ic integrates a pwm controllers, a linear regulator and a linear controller as well as the monitoring and protection functions into a single package. the pwm controller regulates the microprocessor core voltage with a synchronou s-rectified buck converter. the linear controller regulates power for the gtl bus and the linear regulator provides power for the clock driver circuit. the HIP6018B includes an intel-compatible, ttl 5-input digital-to-analog converter (dac) that adjusts the core pwm output voltage from 2.1vdc to 3.5vdc in 0.1v increments and from 1.3vdc to 2.05vdc in 0.05v steps. the precision reference and voltage-mode control provide 1% static regulation. the linear regulator uses an internal pass device to provide 2.5v 2.5%. the linear controller drives an external n-channel mosfet to provide 1.5v 2.5%. the HIP6018B monitors all the output voltages. a single power good signal is issued when the core is within 10% of the dac setting and the other levels are above their under- voltage levels. additional built-in over-voltage protection for the core output uses the lowe r mosfet to prevent output voltages above 115% of the dac setting. the pwm over- current function monitors the output current by using the voltage drop across the upper mosfet?s r ds(on) , eliminating the need for a current sensing resistor. pinout HIP6018B (soic) top view features ? provides 3 regulated voltages - microprocessor core, clock and gtl power ? drives n-channel mosfets ? operates from +3.3v, +5v and +12v inputs ? simple single-loop pwm control design - voltage-mode control ? fast transient response - high-bandwidth error amplifier - full 0% to 100% duty ratios ? excellent output voltage regulation - core pwm output: 1% over temperature - other outputs: 2.5% over temperature ? ttl-compatible 5-bit digital-to-analog core output voltage selection - wide range . . . . . . . . . . . . . . . . . . . 1.3v dc to 3.5v dc - 0.1v steps . . . . . . . . . . . . . . . . . . . . 2.1v dc to 3.5v dc - 0.05v steps . . . . . . . . . . . . . . . . . . 1.3v dc to 2.05v dc ? power-good output voltage monitor ? microprocessor core voltage protection against shorted mosfet ? over-voltage and over-current fault monitors - does not require extra current sensing element, uses mosfet?s r ds(on) ? small converter size - constant frequency operation - 200khz free-running oscillator; programmable from 50khz to over 1mhz applications ? full motherboard power regulation for computers ? low-voltage distributed power supplies vcc vid4 vid3 vid2 rt fb2 vin2 ugate1 ocset1 pgnd lgate1 gnd fb3 vout2 phase1 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 14 13 fault vid1 ss fb1 drive3 vid0 pgood vsen1 comp1 ordering information part number temp. range ( o c) package pkg. no. HIP6018Bcb 0 to 70 24 ld soic m24.3 data sheet march 2003 fn4586.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 block diagram 0.23a 115% 110% 90% inhibit pwm comp error amp vcc pgood pwm gnd vsen1 ocset1 vid0 vid1 vid2 vid3 fb1 comp1 dacout ugate1 phase1 200ma 11 a 4v + - + - + - + - vid4 lgate1 pgnd vout2 drive3 fb3 inhibit rt 0.3v + - + - + - + - 1.26v + - power-on reset (por) oscillator + - gate control vcc vcc vcc ss lower drive upper + - 3v + - under- voltage fb2 linear ov luv oc1 oc2 + - ttl d/a converter (dac) vin2 3v fault soft- start & fault logic drive figure 1. HIP6018B
3 simplified power system diagram typical application pwm1 +5v in v out1 q1 q2 v out2 q3 v out3 linear linear HIP6018B regulator controller controller +3.3v in figure 2. +3.3v in vid1 vid2 vid3 vid4 ss gnd vcc +5v in vid0 +12v in v out1 pgnd vsen1 pgood lgate1 ugate1 ocset1 phase1 q1 q2 powergood fb1 comp1 1.3v to 3.5v drive3 fb3 vout2 c out2 1.5v 2.5v c out3 c in c out1 q3 cr1 l out1 HIP6018B v out3 v out2 fault fb2 c ss rt vin2 figure 3. HIP6018B
4 absolute m aximum ratings thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v pgood, rt, fault, and gate vo ltage . . gnd - 0.3v to v cc + 0.3v input, output or i/o voltage . . . . . . . . . . . . . . . . . . gnd -0.3v to 7v operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . +12v 10% ambient temperature range. . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c junction temperature range . . . . . . . . . . . . . . . . . . . 0 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 maximum junction temperature (plastic package) 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. electrical specifications recommended operating conditions, unless other wise noted. refer to figures 1, 2 and 3 parameter symbol test conditions min typ max units vcc supply current nominal supply i cc ugate1, drive3, lgate1, and vout2 open - 8 - ma power-on reset rising vcc threshold v ocset = 4.5v 8.6 - 10.4 v falling vcc threshold v ocset = 4.5v 8.2 - 10.2 v rising vin2 under-voltage threshold 2.45 2.55 2.65 v vin2 under-voltage hysteresis - 100 - mv rising v ocset1 threshold - 1.25 - v oscillator free running frequency rt = open 185 200 215 khz total variation 6k ? < rt to gnd < 200k ? -15 - +15 % ramp amplitude ? v osc rt = open - 1.9 - v p-p reference and dac dac(vid0-vid4) input low voltage - - 0.8 v dac(vid0-vid4) input high voltage 2.0 - - v dacout voltage accuracy -1.0 - +1.0 % reference voltage (pin fb2 and fb3) 1.240 1.265 1.290 v linear regulator regulation 10ma < i vout2 < 150ma -2.5 - 2.5 % under-voltage level fb2 uv fb2 rising - 75 87 % under-voltage hysteresis - 6 - % over-current protection 180 230 - ma over-current protection during start-up 560 700 - ma linear controller regulation vsen3 = drive3, 0 < i drive3 < 20ma -2.5 - 2.5 % under-voltage level fb3 uv fb3 rising - 75 87 % under-voltage hysteresis - 6 - % output drive current i drive3 vin2 - v out3 > 1.5v 20 40 - ma drive3 source current vin2 - drive3 > 0.6v 20 40 - ma HIP6018B
5 pwm controller error amplifier dc gain - 88 - db gain-bandwidth product gbwp - 15 - mhz slew rate sr comp = 10pf - 6 - v/ s pwm controller gate driver upper drive source i ugate vcc = 12v, v ugate1 (or v gate2 ) = 6v - 1 - a upper drive sink r ugate v ugate1-phase1 = 1v - 1.7 3.5 ? lower drive source i lgate vcc = 12v, v lgate1 = 1v - 1 - a lower drive sink r lgate v lgate1 = 1v - 1.4 3.0 ? protection v out1 over-voltage trip vsen1 rising 112 115 118 % fault sourcing current i ovp v fault = 10v 10 14 - ma ocset1 current source i ocset v ocset = 4.5v dc 170 200 230 a soft-start current i ss - 11 - a chip shutdown soft-start threshold - - 1.0 v power good v out1 upper threshold vsen1 rising 108 - 110 % v out1 under voltage vsen1 rising 92 - 94 % v out1 hysteresis (vsen1 / dacout) upper/lower threshold - 2 - % pgood voltage low v pgood i pgood = -4ma - - 0.5 v electrical specifications recommended operating conditions, unless other wise noted. refer to figures 1, 2 and 3 (continued) parameter symbol test conditions min typ max units typical performance curves figure 4. r t resistance vs frequency figure 5. bias supply current vs frequency 10 100 1000 switching frequency (khz) resistance (k ? ) 10 100 1000 r t pullup to +12v r t pulldown to v ss 100 200 300 400 500 600 700 800 900 1000 0 20 40 60 80 100 switching frequency (khz) i cc (ma) c ugate1 = c lgate1 = c gate c gate = 4800pf c gate = 3600pf c gate = 1500pf c gate = 660pf v vcc = 12v, v in = 5v HIP6018B
6 functional pin description vsen1 (pin 19) this pin is connected to the pwm converter?s output voltage. the pgood and ovp comparator ci rcuits use this signal to report output voltage status and for over voltage protection. ocset1 (pin 20) connect a resistor (r ocset ) from this pin to the drain of the upper mosfet. r ocset , an internal 200 a current source (i ocset ), and the upper mosfet on-resistance (r ds(on) ) set the pwm converter over-c urrent (oc) trip point according to the following equation: an over-current trip cycles the soft-start function. sustaining an over-current for 2 soft-start intervals shuts down the controller. ss (pin 9) connect a capacitor from this pin to ground. this capacitor, along with an internal 11 a (typically) current source, sets the soft-start interval of the converter. pulling this pin low with an open drain signal will shut down the ic. vid0, vid1, vid2, vid3, vid4 (pins 6, 5, 4, 3 and 2) vid0-4 are the input pins to the 5-bit dac. the states of these five pins program the internal voltage reference (dacout). the level of dacout sets the core converter output voltage. it also sets the core pgood and ovp thresholds. comp1 and fb1 (pins 17 and 18) comp1 and fb1 are the available external pins of the pwm error amplifier. the fb1 pin is the inverting input of the error amplifier. similarly, the comp1 pin is the error amplifier output. these pins are used to compensate the voltage- control feedback loop of the pwm converter. gnd (pin 14) signal ground for the ic. all voltage levels are measured with respect to this pin. pgood (pin 7) pgood is an open collector output used to indicate the status of the output voltages. this pin is pulled low when the core output is not within 10% of the dacout reference voltage and the other outputs are below their under-voltage thresholds. the pgood output is open for ?11111? vid code. see table 1. phase1 (pin 23) connect the phase pin to th e pwm converter?s upper mosfet source. this pin is used to monitor the voltage drop across the upper mosfet for over-current protection. ugate1 (pin 24) connect ugate pin to the pwm converter?s upper mosfet gate. this pin provides the gate drive for the upper mosfet. pgnd (pin 21) this is the power ground connection. tie the pwm converter?s lower mosfet source to this pin. lgate1 (pin 22) connect lgate1 to the pwm converter?s lower mosfet gate. this pin provides the gate drive for the lower mosfet. vcc (pin 1) provide a 12v bias supply for the ic to this pin. this pin also provides the gate bias charge for all the mosfets controlled by the ic. rt (pin 10) this pin provides oscillator switching frequency adjustment. by placing a resistor (r t ) from this pin to gnd, the nominal 200khz switching frequency is increased according to the following equation: conversely, connecting a pull-up resistor (r t ) from this pin to vcc reduces the switching frequency according to the following equation: fault (pin 8) this pin is low during normal opera tion, but it is pulled to vcc in the event of an over-volt age or over-current condition. drive3 (pin 15) connect this pin to the gate of an external mosfet. this pin provides the drive for the linear controller?s pass transistor. fb3 (pin 16) connect this pin to a resistor divider to set the linear controller output voltage. vout2 (pin 13) output of the linear regulator. supplies current up to 230ma. fb2 (pin 11) connect this pin to a resistor divider to set the linear regulator output voltage. vin2 (pin 12) this pin supplies power to the internal regulator. connect this pin to a suitable 3.3v source. additionally, this pin is used to monitor the 3.3v supply. if, following a startup cycle, the voltage drops below 2.55v (typically), the chip shuts dow n. a new soft-start cycle is i peak i ocset r ocset r ds on () --------------------------------------------------- - = fs 200khz 510 6 r t k ? () -------------------- - + (r t to gnd) fs 200khz 410 7 r t k ? () -------------------- - ? (r t to 12v) HIP6018B
7 initiated upon return of the 3.3v supply above the under- voltage threshold. description operation the HIP6018B monitors and precisely controls 4 output voltage levels (refer to figures 1, 2, and 3). it is designed for microprocessor computer applications with 3.3v and 5v power, and 12v bias input from an atx power supply. the ic has one pwm controller, a linear controller, and a linear regulator. the pwm controller is designed to regulate the microprocessor core voltage (v out1 ) by driving 2 mosfets (q1 and q2) in a synchronous-rectified buck converter configuration. the co re voltage is regulated to a level programmed by the 5-bit digital-to-analog converter (dac). an integrated linear regulator supplies the 2.5v clock power (v out2 ). the linear controller drives an external mosfet (q3) to supply the gtl bus power (v out3 ). initialization the HIP6018B automatically in itializes upon receipt of input power. special sequencing of the input supplies is not necessary. the power-on reset (por) function continually monitors the input supply vo ltages. the por monitors the bias voltage (+12v in ) at the vcc pin, the 5v input voltage (+5v in ) on the ocset1 pin, and the 3.3v input on the vin2 pin. the normal level on ocset1 is equal to +5v in less a fixed voltage drop (see over-c urrent protection). the por function initiates soft-start operation after all three input supply voltages exceed their por thresholds. soft-start the por function initiates the so ft-start sequence. initially, the voltage on the ss pin rapidl y increases to approximately 1v (this minimizes the soft-start interval). then an internal 11 a current source charges an external capacitor (c ss ) on the ss pin to 4v. the pwm error amplifier reference input (+terminal) and output (comp1 pin) is clamped to a level proportional to the ss pin voltage. as the ss pin voltage slews from 1v to 4v, the output clamp generates phase pulses of increasing width that charge the output capacitor(s). after this initial stage, the reference input clamp slows the output voltage rate-of -rise and provides a smooth transition to the final set voltage. additionally both linear regulator?s reference inputs are clamped to a voltage proportional to the ss pin volt age. this method provides a rapid and controlled output voltage rise. figure 3 shows the soft-start sequence for the typical application. at t0 the ss voltage rapidly increases to approximately 1v. at t1, the ss pin and error amplifier output voltage reach the valley of the oscillator?s triangle wave. the oscillator?s triangular waveform is compared to the clamped error amplifier output voltage. as the ss pin voltage increases, the pu lse-width on the phase pin increases. the interval of increasing pulse-width continues until each output reaches sufficient voltage to transfer control to the input reference cl amp. if we consider the 2.0v output (v out1 ) in figure 3, this time occurs at t2. during the interval between t2 and t3, the error amplifier reference ramps to the final value and the converter regulates the output to a voltage proportional to the ss pin voltage. at t3 the input clamp voltage exceeds the reference voltage and the output voltage is in regulation . the remaining outputs are also programmed to follow the ss pin voltage. each linear output (v out2 and v out3 ) initially follows a ramp simila r to that of the pwm output. when each output reaches suff icient voltage the input reference clamp slows the rate of output voltage rise. the pgood signal toggles ?high? when all output voltage levels have exceeded their under-voltage levels. see the soft-start interval section under applications guidelines for a procedure to determine the soft-start interval. fault protection all three outputs are monito red and protected against extreme overload. a sustai ned overload on any linear regulator output or an over-v oltage on the pwm output disables all converters and dr ives the fault pin to vcc. figure 7 shows a simplified schematic of the fault logic. an over-voltage detected on vsen1 immediately sets the fault latch. a sequence of three over-c urrent fault signals also sets the fault latch. a comparator indicates when c ss is fully charged (up signal), such t hat an under-voltage event on either linear output (fb2 or fb3) is ignored until after the soft- start interval (t4 in figure 6) . at startup, this allows v out2 figure 6. soft-start interval 0v 0v 0v time pgood soft-start (1v/div) output (0.5v/div) voltages v out1 (dac = 2v) v out2 ( = 2.5v) v out3 ( = 1.5v) t1 t2 t3 t0 (2v/div) t4 HIP6018B
8 and v out3 to slew up over increased time intervals, without generating a fault. cycling the bias input voltage (+12v in on the vcc pin) off then on resets the counter and the fault latch. over-voltage protection during operation, a short on the upper pwm mosfet (q1) causes v out1 to increase. when the output exceeds the over-voltage threshold of 115% (typical) of dacout, the over-voltage comparator trips to set the fault latch and turns q2 on as required in order to regulate v out1 to 1.15 x dacout. this blows the input fuse and reduces v out1 . the fault latch raises the fault pin close to vcc potential. a separate over-voltage circuit provides protection during the initial application of power . for voltages on the vcc pin below the power-on reset (and above ~4v), v out1 is monitored for voltages exceeding 1.26v. should vsen1 exceed this level, the lower mosfet (q2) is driven on as needed to regulate v out1 to 1.26v. over-current protection all outputs are prot ected against excess ive over-currents. the pwm controller uses the upper mosfet?s on- resistance, r ds(on) to monitor the current for protection against shorted outputs. the linear regulator monitors the current of the integrated power device and signals an over- current condition for currents in excess of 230ma. additionally, both the linear regulator and the linear controller monitor fb2 and fb3 for under-voltage to protect against excessive currents. figures 8 and 9 illustrate the over-current protection with an overload on out1. the overload is applied at t0 and the current increases through the output inductor (l out1 ). at time t1, the over-current1 compar ator trips when the voltage across q1 (i d ? r ds(on) ) exceeds the leve l programmed by r ocset . this inhibits all outputs, discharges the soft-start capacitor (c ss ) with a 11 a current sink, and increments the counter.c ss recharges at t2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. with out1 still overloaded, the inductor current increases to trip the over- current comparator. again, this inhibits all outputs, but the soft-start voltage continues increasing to 4v before discharging. the coun ter increments to 2. the soft-start cycle repeats at t3 and trips the over-current comparator. the ss pin voltage increases to 4v at t4 and the counter increments to 3. this sets the fault latch to disable the converter. the fault is reported on the fault pin. the linear regulator operates in the same way as pwm1 to over-current faults. additionally, the linear regulator and linear controller monitor the feedback pins for an under- voltage. should excessive currents cause fb2 or fb3 to fall below the linear under-voltage threshold, the luv signal sets the over-current latch if c ss is fully charged. blanking the luv signal during the c ss charge interval allows the linear outputs to build above the under-voltage threshold during normal start-up. cy cling the bias input power off then on resets the counter and the fault latch. resistor r ocset1 programs the over-current trip level for the pwm converter. as shown in figure 9, the internal 200 a current sink develops a voltage across r ocset (v set ) that is referenced to v in . the drive signal enables the over-current comparator (over-current1). when the voltage across the upper mosfet (v ds(on) ) exceeds v set , the over-current comparator trips to set the over-current latch. both v set and v ds are referenced to v in and a small capacitor across r ocset helps v ocset track the variations of v in due to mosfet switching. the over-curre nt function will trip at a peak inductor current (i peak) determined by: fault latch s r q por counter oc1 ov luv + - + - 0.15v 4v ss vcc fault r figure 7. fault logic - simplified schematic up over current latch inhibit s r q s inductor current soft-start 0a 0v 2v 4v figure 8. over-current operation time t1 t2 t3 t0 t4 fault/rt 0v 10v overload applied count = 1 count = 2 count = 3 fault reported i peak = i ocset xr ocset r ds on () ------------------------------------------------------ - HIP6018B
9 the oc trip point varies with mo sfet?s temperature. to avoid over-current tripping in the normal operating load range, determine the r ocset resistor from t he equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine i peak for i peak > i out(max) + ( ? i) / 2, where ? i is the output inductor ripple current. for an equation for the output inductor ripple current see the section under component guidelin es titled ?output inductor selection?. out1 voltage program the output voltage of the pwm converter is programmed to discrete levels between 1.3v dc and 3.5v dc . this output is designed to supply the microprocessor core voltage. the voltage identification (vid) pins program an internal voltage reference (dacout) through a ttl-compatible 5-bit digital-to-analog converter. the level of dacout also sets the pgood and ovp threshol ds. table 1 specifies the dacout voltage for the different combinations of connections on the vid pins. the vid pins can be left open for a logic 1 input, because they are internally pulled up to +5v by a 10 a (typically) current s ource. changing the vid inputs during operation is not recommended. the sudden change in the resulting reference voltage could toggle the pgood signal and exercise the over-voltage protection. the ?11111? vid pin combination resulting in an inhibit disables the ic and the open-c ollector at the pgood pin. ugate ocset phase over- current1 + - gate control vcc oc1 200 a v ds i d v set r ocset v in = +5v over-current trip: v ds > v set (i d ? r ds (on) > i ocset ? r ocset ) i ocset + + figure 9. over-current detection pwm v phase = v in - v ds v ocset = v in - v set drive HIP6018B vcc lgate pgnd table 1. v out1 voltage program pin name nominal out1 voltage dacout vid4 vid3 vid2 vid1 vid0 0 1 1 1 1 1.30 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 0 1 0 0 1 1.60 0 1 0 0 0 1.65 0 0 1 1 1 1.70 0 0 1 1 0 1.75 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 inhibit 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 1 0 1 1 1 2.8 1 0 1 1 0 2.9 1 0 1 0 1 3.0 1 0 1 0 0 3.1 1 0 0 1 1 3.2 1 0 0 1 0 3.3 1 0 0 0 1 3.4 1 0 0 0 0 3.5 note: 0 = connected to gnd or v ss , 1 = open or connected to 5v through pull-up resistors. HIP6018B
10 application guidelines soft-start interval initially, the soft-start function cl amps the error amplifier?s output of the pwm converter. after th e output voltage increases to approximately 80% of the set value, the reference input of the error amplifier is clamped to a voltage proportional to the ss pin voltage. both linear outputs follo w a similar start-up sequence. the resulting output voltage sequence is shown in figure 6. the soft-start function controls the output voltage rate of rise to limit the current surge at star t-up. the soft-start interval is programmed by the soft-start capacitor, c ss . programming a faster soft-start interval in creases the peak surge current. the peak surge current occurs during the initial output voltage rise to 80% of the set value. shutdown the pwm output does not switch until the soft-start voltage (v ss ) exceeds the oscillator?s valley voltage. additionally, the reference on each linear?s amplifier is clamped to the soft-start voltage. holding the ss pin low with an open drain or collector signal turns off all three regulators. the vid codes resulting in an inhibit as shown in table 1 also shuts down the ic. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one device to another causes voltage spikes across the interconnec ting impedances and parasitic circuit elements. the voltage sp ikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. consider, as an example, the turn-off transition of the upper pwm mosfet. prior to turn-off, the upper mosfet was carrying the full load current. during the turn-off, curr ent stops flowing in the upper mosfet and is picked up by the lower mosfet (and/or parallel schottky diode). any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, ti ght layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. cont act intersil for evaluation board drawings of the component placement and printed circuit board. there are two sets of critical components in a dc-dc converter using a HIP6018B controller. the power components are the most critical because they swit ch large amounts of energy. the critical small signal components connect to sensitive nodes or supply critical by-passing current. the power components should be placed first. locate the input capacitors close to the power switches. minimize the length of the connections between the input capacitors and the power switches. locate the output inductor and output capacitors between the mosfets and the load. locate the pwm controller close to the mosfets. the critical small signal components include the by-pass capacitor for vcc and the soft-start capacitor, c ss . locate these components close to their connecting pins on the control ic. minimize any leakage current paths from ss node because the internal current source is only 11 a. a multi-layer printed circuit board is recommended. figure 10 shows the connections of the critical components in the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. the power plane should support the input po wer and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the control ic to the mosfet gat e and source should be sized to carry 1a currents. the traces for out2 need only be sized for 0.2a. locate c out2 close to the HIP6018B ic. pwm controller feedback compensation both pwm controllers use voltage-mode control for output regulation. this section high lights the design consideration for a voltage-mode controller. apply the methods and considerations to both pwm controllers. figure 11 highlights the voltage-mode control loop for a synchronous-rectified buck conver ter. the output voltage is regulated to the reference voltage level. the reference voltage level is the dac output voltage for the pwm controller. the error amplifier output (v e/a ) is compared with the oscillator (osc) triangular wave to provide a pulse-width modulated wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). v out1 q1 q2 c ss +12v c vcc load via connection to ground plane island on power plane layer island on circuit plane layer l out1 c out1 cr1 load c in v out3 +5v in figure 10. printed circuit board power planes and islands key HIP6018B ss pgnd lgate1 ugate1 phase1 gate3 vcc gnd vin2 +3.3v in q3 load c out2 v out2 vout2 ocset1 r ocset1 c ocset1 HIP6018B
11 the modulator transfer function is the small-signal transfer function of v out /v e/a . this function is dominated by a dc gain and the output filter, with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage, v in , divided by the peak-to-peak oscillator voltage, ? v osc . modulator break frequency equations the compensation network consis ts of the error amplifier internal to the HIP6018B and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with an acceptable 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 degrees . the equations below relate the compensation network?s poles, zeros and gain to the components (r1 , r2 , r3 , c1 , c2 , and c3) in figure 11. use these guidelines for locating the poles and zeros of the compensation network: 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1 st zero below filter?s double pole (~75% f lc ) 3. place 2 nd zero at filter?s double pole 4. place 1 st pole at the esr zero 5. place 2 nd pole at half the switching frequency 6. check gain against error amplifier?s open-loop gain 7. estimate phase margin - repeat if necessary compensation break frequency equations figure 12 shows an asymptotic plot of the dc-dc converter?s gain vs. frequency. the actual modulator gain has a peak due to the high q factor of the output filter at f lc , which is not shown in figure 12. using the abo ve guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the log-log graph of figure 12 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance networks z fb and z in to provide a stable, high bandwidth loop. a stable control loop has a 0db gain crossing with -20db/decade slope and a phase margin greater than 45 degrees. include worst case component variations when determining phase margin. component selection guidelines output capacitor selection the output capacitors for each output have unique requirements. in general the output capacitors should be selected to meet the dynamic regulation requirements. additionally, the pwm conver ters require an output capacitor to filter the current ripple. the linear regulator is internally compensated and requires an output capacitor that meets the stability requirements. the load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. figure 11. voltage-mode buck converter compensation design v out osc reference l o c o esr v in ? v osc error amp pwm driver (parasitic) z fb + - reference r1 r3 r2 c3 c2 c1 comp v out fb z fb HIP6018B z in comp driver detailed feedback compensation phase v e/a + - + - z in f lc 1 2 l o c o --------------------------------------- - = f esr 1 2 esr c o ----------------------------------------- = f z1 1 2 r 2c1 ----------------------------------- = f z2 1 2 r1 r3 + () c3 ------------------------------------------------------ - = f p1 1 2 r 2 c1 c2 c1 c2 + ---------------------- ?? ?? ------------------------------------------------------- = f p2 1 2 r 3c3 ----------------------------------- = 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 20log f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / ? v osc ) modulator gain (r 2 /r 1 ) figure 12. asymptotic bode plot of converter gain closed loop gain HIP6018B
12 pwm output capacitors modern microprocessors produce transient load rates above 10a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor valu es are generally determined by the esr (effective series resistance) and esl (effective series inductance) pa rameters rather than actual capacitance. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching regulator applications for the bulk capacitors. the bulk capacitor?s esr determines the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor?s esr val ue is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedanc e with frequency to select suitable components. in most cases, multiple electrolytic capacitors of small ca se size perform better than a single large case capacitor. for a given transient load magnitude, the output voltage transient response due to the output capacitor characteristics can be approxim ated by the following equation: linear output capacitors the output capacitors for the linear regulator and the linear controller provide dynamic load current. the linear controller uses dominant pole compensatio n integrated in the error amplifier and is insensitive to output capacitor selection. capacitor, c out3 should be selected for transient load regulation. the output capacitor for the linear regulator provides loop stability. the linear regulator (out2) requires an output capacitor characteristic shown in figure 13. the upper line plots the 45 phase margin with 150ma load and the lower line is the 45 phase margin limit with a 10ma load. select a c out2 capacitor with characteristic between the two limits. output inductor selection the pwm converter requires an output inductor. the output inductor is selected to meet the output voltage ripple requirements and sets the converter?s response time to a load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following equations: increasing the value of inductance reduces the ripple current and voltage. however, the large inductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fa st control loop design, the HIP6018B will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the post-transi ent current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitors. minimizing the resp onse time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and removal of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time can be either at the application or removal of load, and dependent upon the output voltage setting. be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. input capacitor selection the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. v tran esl di tran dt -------------------- - esr i tran + = 10 1000 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 capacitance ( f) esr ( ? ) figure 13. c out2 output capacitor s t a b l e o p e r a ti o n ? i v in v out ? f s l o ------------------------------- - v out v in --------------- - = ? v out ? iesr = t rise l o i tran v in v out ? ------------------------------- - = t fall l o i tran v out ------------------------------ - = HIP6018B
13 use a mix of input bypass capac itors to contro l the voltage overshoot across the mosfet s. use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors should be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for a through hole design, seve ral electrolytic capacitors (panasonic hfq series or nichicon pl series or sanyo mv- gx or equivalent) may be needed. for surface mount designs, solid tantalum capacit ors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx, and the 593d series from sprague are both surge current tested. mosfet selection/considerations the HIP6018B requires 3 n-channel power mosfets. two mosfets are used in the synchronous-rectified buck topology of the pwm converter. the linear controller drives a mosfet as a pass transistor. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. pwm1 mosfet selection and considerations in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty factor (see the equations below). the conduction loss is the only component of power dissipation for the lower mosfet. only the upper mosfet has switching losses, since the lower device tu rns on into near zero voltage. the equations below assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfet?s body diode. the gate-charge losses are proportional to the switching frequency (f s ) and are dissipated by the HIP6018B, thus not contributing to the mosfets? temperature rise. however, la rge gate charge increases the switching interval, t sw which increases the upper mosfet switching losses. ensu re that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the r ds(on) is different for the two pr evious equations even if the type device is used for both. this is because the gate drive applied to the upper mosfet is different than the lower mosfet. figure 14 shows the gate drive where the upper gate- to-source voltage is approximately v cc less the input supply. for +5v main power and +12vdc for the bias, the gate-to-source voltage of q1 is 7v. the lower gate drive voltage is +12vdc. a logic-level mosfet is a good choice for q1 and a logic-level mosfet can be used for q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to v cc . rectifier cr1 is a clamp that catches the negative inductor voltage swing during the dead time between the turn off of the lower mosfet and the turn on of the upper mosfet. the diode must be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. it is acceptable to omit the diode and let the body diod e of the lower mosfet clamp the negative inductor swing, but efficiency might drop one or two percent as a result. the diode's rated reverse breakdown voltage must be greater than twice the maximum input voltage. linear controller mosfet selection the main criteria for the selecti on of a transistor for the linear regulator is package selection for efficient removal of heat. the power dissipated in a linear regulator is: select a package and heatsink that maintains the junction temperature below the maximum rating while operating at the highest expected ambient temperature. additionally, if selecting a bipolar npn transistor, insure the gain (h fe ) at the minimum operating temperature and given collector-to-emitter voltage is sufficiently high as to deliver the worst-case steady st ate current required by the gtl output, when the transistor is driven with the minimum guaranteed drive3 output current. for example, operating at ?t? junction temperature, 3.3v input, and 1.5v output (v ce = 1.8v) the npn?s gain should satisfy the following equation: p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f s 2 ---------------------------------------------------- + = p lower i o 2 r ds on () v in v out ? () v in -------------------------------------------------------------------------------- - = +12v pgnd HIP6018B gnd lgate ugate phase v cc +5v or less note: note: v gs v cc q1 q2 + - figure 14. output gate drivers v gs v cc -5v cr1 p linear i o v in v out ? () = h fe i gtl steady state ? () i drive3 min () ---------------------------------------------------------- - > HIP6018B
14 HIP6018B dc-dc converte r application circuit figure 15 shows an application circuit of a power supply for a microprocessor computer system. the power supply pro - vides the microproce ssor core voltage (v out1 ), the gtl bus voltage (v out3 ) and clock generator voltage (v out2 ) from +3.3v dc , +5v dc and +12v dc . for detailed information on the circuit, including a bill-of-materials and circuit board description, see application note an9805. also see intersil?s web page (http://www.intersil.com) or intersil answerfax (321-724-7800) document # 99805 for the latest information. vid1 vid2 vid3 vid4 ss gnd vcc +5v in vid0 +12v in pgnd vsen1 pgood lgate1 ugate1 ocset1 phase1 q1 q2 powergood fb1 comp1 vin2 drive3 fb3 vout2 fb2 c47 v out3 v out2 c43-46 c24-36 HIP6018B q3 l3 + + + + + c16 l1 f1 c1-7 c15 c18 r2 v out1 r4 r8 c40 c41 c42 r10 r9 c48 r11 r12 r13 r14 270 f 4x1000 f c19 1000 f 1 h 6x1000 f 1 f 1 f 1000pf huf76143 huf76143 7x1000 f 0.039 f 1.1k 3.5 h 0.68 f 10pf 2200pf 4.99k 2.21k 160k 732k gnd 1.87k 10k 10k 10k rfd3055 vid1 vid2 vid3 vid4 vid0 (1.3 to 3.5v) (1.5v) (2.5v) 15a fault 1 20 7 24 23 22 21 19 18 12 17 14 8 11 13 9 3 4 5 6 16 15 +3.3v in 2 figure 15. application circuit 10 rt HIP6018B
15 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HIP6018B small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 o 8 o 0 o 8 o - rev. 0 12/93

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